This invention relates, in general, to semiconductor processing and, more specifically, to forming a dielectric between metal structures.
As integrated circuit (IC) device dimensions shrink, spacing between metal lines is reduced leading to higher parasitic capacitance and consequently, increased signal delay. This has led to the development of low dielectric constant (low-K) materials for use as the dielectric between these metal lines. As used herein, low-K materials refer to materials with dielectric constants less than that of silicon dioxide, which is about 4.0. Low-K materials are often less than 3.5 or even less than 3.0. High-K materials refer to materials with dielectric constants greater than that of silicon dioxide and are commonly greater than 4.2 or even greater than 4.5. With low-k materials being used to decrease the parasitic capacitance, some problems have been encountered. For example, low-K materials suffer from lower mechanical strength than conventional higher-K materials. In addition, many low-K materials do not adequately adhere to other conventional IC materials. Unlike traditional dielectric materials, patterning low-K materials results in deformed etch profiles due to the material""s mechanical and thermal instability. One solution is to use a patternable dielectric layer to form metal structures and subsequently remove the dielectric layer and replace the patternable dielectric layer with a low-K dielectric. The replacement low-K dielectrics, however, have been found to result in reduced mechanical strength and poor adhesion. Therefore, a process for replacing the patternable dielectric layer with a low-K dielectric that does not decrease mechanical strength and does not have poor adhesion is needed.